Semiconductor devices and circuits are prone to aging-related wear-out, leading to performance degradation and circuit failure. Characterizing and margining for aging are critical for delivering high-quality products. I/O circuits in semiconductor chips need to operate at higher voltages for compatibility with chips made with older-generation technologies. On advanced nodes, higher-voltage devices cannot be built due to scaling challenges. Therefore, such circuits are made by stacking lower-voltage devices. If the voltage division is not uniform, asymmetric wear-out and premature circuit failure can occur.
Functional Data Explorer is used to analyze chemical spectra. Here, FDE has been extended to model the change in the falling edge of the output waveform of a 3.3 V I/O test circuit, built using native 1.8 V devices, due to hot-carrier injection in a device of the stacked pair. Conventionally, a parametric reliability model is generated for the degradation of the output low current (IOL), which is then translated into an application parameter (fall time). With FDE, the changes in the waveform and fall time can directly be determined. The use of functional principal components allows the system to be represented by fewer parameters, which can help streamline the model and predictability.
