Uncovering Hidden Gems in Semiconductor Manufacturing with JMP Map Shapes (2025-US-PO-2497)

Every wafer we build is a keeper of secrets, tiny patterns that can make or break yield. For over a decade, JMP has been a key item in my toolbox for uncovering these secrets.

I'm Jason Paquette, a Product Development Engineer at AMD, and today I would like to show you how JMP has helped my team and I uncover hidden signals and drive real change. A quick disclaimer upfront. All of the data that I've put together for this presentation has been simulated for illustrative purposes only, solely to satisfy our legal team to be able to present here.

In my role, about 90% of my time is spent digging through product test data, looking for yield improvement opportunities. The reason for this is simply because wafer fabrication is one of the largest costs for our company, and even fractional points of yield improvement can amount to millions of dollars in cost savings. Yield loss itself can happen for a variety of reasons, but today I would like to simply focus on systematic defects that occur during wafer fabrication.

During wafer fabrication, wafers go through hundreds of extremely precise steps where defects can occur due to particle contamination, process variation, equipment misalignment or miscalibration, or even design sensitivities, just to name a few.

If we look at the center of the poster, I have what we call a wafer map. And this has been generated using JMP Map Shapes visualized within the Graph Builder platform. Each tiny little rectangle on the wafer map that I've blown up in this larger red rectangle is known as a die, which is essentially just an unpackaged chip. The standard way that we visualize defect data spatially is by stacking wafer maps on top of each other to show the average pass/fail result for each die location across many wafers. In this particular case, I chose JMP's lovely black body radiation color scheme that depicts low yielding areas as light and high yielding areas as dark. These dye level wafer maps are great tools for spotting large scale patterns, like the ones you might be able to see yourself in the bullseye and on the edge. But unfortunately, this falls short for very fine signatures, especially when the product die size start to get quite large.

To get around this, we can actually go deeper. Instead of just using pass/fail results at the die level, we can look at sub-die level results, where we call these sub-die level structures, tiles. Each die is composed of many tiles, each with their own specific functionality and our ability to test them individually. With the use of our design layout database, we are able to extract the coordinate information for all the vertices of these tiles and generate map shape files for displaying tile fail rates spatially within Graph Build. An example of this can be seen in the top right with a tile floor plan and a breakout of what one of these odd-shaped tiles looks like.

This does greatly improve our granularity situation, but it does have some notable limitations. The first limitation is that what we call random defectivity is not accounted for using this simple tile fail rate or yield data. This is because tiles themselves don't have a standard or consistent density. They actually vary quite widely. Simply put, tiles with higher circuit density will have a larger probability of a random defect falling on them than tiles that have less density. If we don't correct for this, normal variation itself could be interpreted as outlier signatures, and even true outliers that we're looking for might just be buried in the noise.

To address this, we compute what we call a critical area, again, using our design database. For each tile, I normalize our tile fail data using the Poisson yield model equation that I've got on the slide here. This gives us a true defect density by area to best represent what is really going on. The second limitation that we're faced with is that spatial data itself is typically analyzed on a product-by-product basis. Different products have different dye sizes, different shape, and different tile placements. This makes direct comparison across products quite difficult.

Without being able to directly compare products in a standardized way, common signatures often go undetected and unnoticed. On their own, outlier signatures may even look weak or like noise. But what if we could combine them all together?

Here's our approach to do this. First, we create standardized map shape files of a wafer map with a fine one-millimeter squared grid using a JSL script that I wrote in the top left right here, entering this lovely, very fine wafer map. Next, we calculate the area overlap between product tiles and the standardized map grid. In this case, we made use of a very handy package in Python called Shapely to perform this. Lastly, we join in all of the previously calculated tile density data, and we scale it by each tile's overlap contribution for each given grid square on the wafer map. Thus, we're able to generate a standardized defect density wafer map.

If we look at the top right, we see a distribution chart showing the overlap area within all of these square grids. It's quite clear that there are a significant portion of grid squares that only partially overlap with the product tiles. This occurs because the uniform grid, not only overlapping with the tiles that we want, it also overlaps with all these thin areas that are between die and at the perimeter of the die that we don't really care so much about. For better accuracy in our defect density maps, we will omit those grid spaces from our further analysis.

With all the nuts and bolts out of the way, let's just take a look at what the results show.

Shown on the left are four fictitious product defect density maps that have been generated, each on their own, quite faint body, some with some signatures that might be more obvious than others, but key features are missing, leaving the complete picture less than whole. The magic of this whole approach comes together when we superimpose all of the products together into a single defect density map, causing all of the hidden gems to reveal themselves, clear as day.

I know that this is all simulated data, but isn't this a cool picture? Isn't this neat? I think so. For those curious, all of these signatures were created using a fun little mix of JMP's random and trigonometric formula functions with the odd bit of tweaking here and there to make things look a bit more presentable for the presentation.

Using this method, we've been able to detect very subtle defects signatures that would have otherwise gone completely unnoticed. And more importantly, the clarity of those signals has given process engineers at our manufacturing partners solid footing on where to focus their debug, leading to faster and more targeted corrective action. Also, the fact that data from multiple products contributes to the same collective observations makes the messaging to our partners that much more powerful.

While this project was focused specifically on semiconductor data, this approach could apply to a wide variety of other applications, specifically if you have any type of spatial data that you can use.

This is the end of my presentation. I do thank you so much for taking the time to listen to it, and I hope you found it interesting. Please don't hesitate to reach out if you have any comments or questions. I'd be happy to speak with you.