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Assessment of Dielectric Reliability in Semiconductor Manufacturing

Reliability assessment of devices and interconnects in semiconductor technologies is typically done for technology certification and periodic monitoring, using relatively small (single digit to tens) sample sizes per condition. Volume manufacturing data can be used over time to assess dielectric reliability by ramped voltage-breakdown measurements on scribe-lane test structures. Over time, this can provide a detailed view of dielectric behavior, including a mixture of intrinsic and extrinsic mechanisms affecting dielectric integrity. In particular, low failure-rate outliers or tails can be detected and addressed, which may otherwise pose field-quality risks.

For practical reasons, the ramp may be stopped at a target voltage to reduce test time and avoid damage to probe cards and needles, which may result in a small number of data points being censored. Fitting large data sets with a small number of censored data points can lead to convergence challenges, resulting in incorrect fitting parameters and lack of confidence intervals, as well as posing significant computational challenges.

This work explores these challenges with the JMP Life Distribution platform and examines alternatives and solutions to allow correct analysis, fitting, and extrapolation.