Application-based Empirical Modeling of Semiconductor Circuit Reliability (2026-US-30MP-2921)

With aggressive technology scaling and novel device architectures in modern semiconductor technologies, it has become challenging to make input/output (I/O) transistors that can support higher voltages (e.g., 3.3 V). However, I/O operation at higher voltages is needed to allow the chip to communicate with other devices on the board, which may have been fabricated with older-generation technologies and may be able to natively support the higher voltages. To accomplish this, I/O circuits in advanced semiconductor devices are built using stacked lower-voltage transistors (e.g., two 1.8 V transistors stacked to support 3.3 V operation), in which the higher voltage is divided across the transistors in the stack such that no individual transistor exceeds the rated voltage specification of the technology. If not optimized in design, these types of circuits are prone to premature wear-out and failure, posing a significant field reliability risk.

This work presents a novel approach for the modeling of reliability degradation in a stacked-device I/O circuit test structure fabricated in an advanced CMOS technology node. A large experimental study was done to generate a multivariate model using conventional reliability parameters, circuit settings, and board elements to provide an application-level degradation profile. The generated model has been validated against application data. The approach can be readily applied to other circuits, applications, and parameters.

The presentation shows how JMP can be used for application-based modeling of semiconductor circuit reliability using empirical product data to assess and manage field risk.