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Staff (Retired)

Using JMP® with Data Structures Common to Semiconductor Manufacturing

 Using JMP® with Data Structures Common to Semiconductor Manufacturing


Joel Dobson, Senior Statistician, Texas Instruments

The front-end manufacturing of IC chips is by lots consisting of silicon wafers in factories called wafer fabs. A typical fab lot might contain 25 wafers. Each wafer may have thousands of chips in a rectangular array. A natural hierarchical structure for the data exists, with chips nested in wafers and wafers nested in lots. The back-end manufacturing of IC chips occurs at assembly and test (A/T) sites. The chips are sawed to separate them from the wafer and assembly lots are formed. Assembly lots may contain chips from separate wafers, but rarely from separate fab lots. The data hierarchy resulting from assembly processes adds to that of the wafer fab. Given the data structure described above, the modeling of critical parameters can present significant challenges. This presentation will review some of the pitfalls and risks associated with following the simple textbook analyses for people who work in semiconductor manufacturing, and show the more appropriate alternatives. Our approach will be largely didactic through live case studies in JMP.

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