Accelerating Power MOSFET Development Using TCAD Simulations and JMP Bayesian Optimization (2026-EU-PO-2837)

In the fast-paced development of new power device technologies, defining and validating robust process windows for key manufacturing modules is critical – but time-consuming. Traditional experimental learning cycles can extend project timelines significantly.

This presentation showcases an innovative approach that combines TCAD simulation data with JMP’s cutting-edge Bayesian Optimization platform to efficiently pinpoint the optimal working point for a new generation of power MOSFETs – minimizing the need for extensive on-silicon learning cycles.

By employing a Gaussian process model built from TCAD simulations, and utilizing JMP’s Design Space Profiler, we thoroughly explored response surfaces across the factor space to identify in-spec regions for all critical performance parameters. This data-driven strategy guided the design of the first physical experiment via JMP’s Custom Designer, ensuring a focused and efficient experimental plan.

As electrical test data becomes available, it will be integrated to refine and validate the predictive model, enhancing its accuracy and enabling faster, smarter decision making in technology platform development.

This work highlights the power of combining advanced simulation with JMP’s flexible analytics to accelerate innovation and reduce development risk in semiconductor manufacturing.